基于CPLD的锁相位同步信号提取技术

详细信息

Getting Technology of Bit Alignment Signal of Phase-locked Loop Based on CPLD

1.
College of Information and Electrical Engineering of CUMT., Xuzhou 221008, China

摘要: 锁相位同步提取技术是通信系统中一个重要的实际问题。现介绍一种用CPLD复杂可编程逻辑器件为控制核心 ,采用AHDL语言编程实现数字锁相位同步信号提取的方法。使整体设计、功能实现更加稳定、可靠。
- 通信系统 /
- 数字锁相环 /
- 位同步信号 /
- CPLD /
- AHDL
Abstract: The technology of getting the bit alignment signal of phase-locked loop is a very important practical problem in communications system. This paper introduced a system to pick up the bit alignment signal of digital phase-locked loop which is programmed in AHDL language and its CPU is CPLD (Complicated Programmable Logic Device). Using this technology, the system will be more stable and credible in its configuration design and function realization.
- communication system /
- DPLL /
- bit alignment signal /
- CPLD /
- AHDL